Recently, the team of Professor Wu Huaqiang and Associate Professor Gao Bin of the School of Integrated Circuits at Tsinghua University developed the world's first fully system-integrated memristor memory and calculation integrated chip that supports efficient on-chip learning (machine learning can be completed directly on the hardware side) based on the integrated storage and calculation computing paradigm. It has made a major breakthrough in the field of memristor memory and calculation integrated chips that support on-chip learning, and is expected to promote the development of artificial intelligence, autonomous driving wearable devices and other fields. Relevant results were published online in the latest issue of "Science".
Current international relevant research mainly focuses on the demonstration of learning functions at the memristor array level. However, the realization of a fully system-integrated memristor chip that supports efficient on-chip learning still faces great challenges and has not yet been realized. The main reason is that the high-precision weight update method required by the traditional backpropagation training algorithm has poor adaptability to the actual characteristics of the memristor.
It is understood that facing the major challenge of traditional storage and computing separation architecture that restricts the improvement of computing power, Wu Huaqiang and Gao Bin creatively proposed a new universal algorithm and architecture (STELLAR) that adapts memristor storage and computing integration to achieve efficient on-chip learning. It effectively realizes monolithic three-dimensional integration of large-scale analog memristor arrays and CMOS. Through the collaborative innovation of the entire process of algorithm, architecture, and integration methods, they developed the world's first fully system-integrated memristor storage and computing integrated chip that supports efficient on-chip learning.
The chip contains all circuit modules necessary to support complete on-chip learning. It has successfully completed various on-chip incremental learning function verifications such as image classification, speech recognition and control tasks. It has demonstrated high adaptability, high energy efficiency, high versatility, high accuracy and other characteristics, effectively strengthening the learning adaptability of smart devices in practical application scenarios. Under the same task, the chip's energy consumption for on-chip learning is only 3% of that of an application-specific integrated circuit (ASIC) system under advanced technology. It shows excellent energy efficiency advantages and has great application potential to meet the high computing power needs of the artificial intelligence era. It provides an innovative development path to break through the energy efficiency bottleneck under the traditional von Neumann computing architecture.
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