In addition to announcing that the next generation of HBM3E high-bandwidth memory can achieve a world-leading 36GB single chip and an equivalent frequency of 9.8GHz, Samsung also looks forward to the direction of a truly new generation of HBM4 memory. In Samsung's plan, HBM4 will have two development directions, using more advanced transistor processes and more advanced packaging technology.
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In terms of technology, Samsung plans to abandon traditional planar transistors and use FinFET three-dimensional transistors on HBM, thereby reducing the required drive current and improving energy efficiency.
FinFET three-dimensional transistor technology was first introduced by Intel22nm and has been the foundation of the semiconductor manufacturing process over the years. Next, Intel20A, TSMC 2nm, and Samsung 3nm will all turn to full surround three-dimensional gate transistors.
In terms of packaging, Samsung plans to shift from micro-bump bonding to bumpless bonding (bumplessbongding) to directly interconnect copper layers.
In fact, this is also quite advanced technology in the field of logic chips and is still under development.
Obviously, these will help HBM memory continue to expand capacity, frequency and bandwidth, but the cost will also remain high, which is destined to have little relevance to ordinary users and will remain exclusive to the HPC and AI fields.