Innovative new chip technology integrates data storage and processing functions, greatly improving efficiency and performance. The chips, inspired by the human brain, are expected to be commercially available within three to five years and will require interdisciplinary collaboration to meet industry safety standards.
Hussam Amrouch has developed an architecture for artificial intelligence that is twice as powerful as comparable in-memory computing methods. According to Nature magazine, the professor at the Technical University of Munich (TUM) applied a new computing paradigm using special circuits called ferroelectric field-effect transistors (FeFETs). Within a few years, this may prove applicable to generative artificial intelligence, deep learning algorithms, and robotics applications.
The basic idea is simple: Where previous chips performed calculations only on transistors, now they are also where data is stored. This saves both time and effort. "As a result, the performance of the chip has also been improved," said Hussam Amrouch, professor of artificial intelligence processor design at the Technical University of Munich (TUM).
Future chips must be faster and more efficient than earlier chips. Therefore, they cannot heat up too quickly. This is crucial if you want to support applications such as real-time computing in scenarios such as drone flight. For a computer, such a task is extremely complex and energy-consuming.
These key requirements for the chip can be summarized by the mathematical parameter TOPS/W: "terahertz operations per second per watt". This can be seen as an important technical indicator of future chips: how many teraflops of operations (TOP) a processor can perform per second (S) when provided with one watt (W) of power.
The new artificial intelligence chip developed by Bosch in cooperation with Fraunhofer IMPS is supported by the American company GlobalFoundries during the production process and can provide 885TOPS/W. That makes it twice as powerful as similar AI chips, including Samsung's MRAM chips. The running speed of currently commonly used CMOS chips is between 10-20TOPS/W. The results of a recent study published in the journal Nature prove this.
Chip architecture inspired by the human brain
The researchers borrowed principles for modern chip architecture from humans. "In the brain, neurons process signals and synapses remember this information," said Amruchi, describing how humans are able to learn and recall complex relationships.
For this purpose, the chip uses "ferroelectric" (FeFET) transistors. This electronic switch has a special additional property (reversal of polarity when voltage is applied) that allows it to store information even when the power supply is cut off. In addition, they enable simultaneous storage and processing of data within the transistor.
"We can now build efficient chipsets for applications such as deep learning, generative artificial intelligence or robotics, for example, where data must be processed where it is generated," Amruchi believes.
The road to market-oriented chips
The researchers aim to use the chip to run deep learning algorithms that identify objects in space or process data generated by drones during flight without experiencing time lag. However, professors from the Munich Institute for Integrated Robotics and Machine Intelligence (MIRMI) at the Technical University of Munich believe that it will take several years to achieve this goal. He believes that the first memory chip suitable for practical applications will not be available until three to five years at the earliest.
One reason is the safety requirements of industry. For example, until the automotive industry adopts this technology, reliable functionality alone will not be enough. It must also meet the industry’s specific standards. "This once again highlights the importance of interdisciplinary collaboration with researchers from different disciplines such as computer science, informatics and electrical engineering," said hardware expert Amruchi. He sees this as a major advantage of MIRMI.