Fujitsu has previewed its next-generation Monaka processor, a 144-core processor suitable for data centers. The Monaka processor was developed in partnership with Broadcom and uses an innovative 3.5DeXtremeDimension system-in-package architecture with four 36-core chips manufactured using TSMC's N2 process.
The chips are stacked face-to-face with SRAM tiles via hybrid copper bonding, and the cache layer uses TSMC's N5 process. A distinctive feature of Monaka's design is its approach to memory architecture. Instead of using HBM, Fujitsu has chosen to use a pure cache memory chip underneath the computing logic, which is compatible with DDR5 DRAM and may utilize advanced modules such as MR-DIMM and MCR-DIMM.
The processor's I/O chip supports the most advanced interfaces, including DDR5 memory, PCIe6.0 and CXL3.0, for seamless integration with modern data center infrastructure. Armv9-A’s confidential computing architecture enhances workload isolation, ensuring security by design.
Fujitsu has set ambitious goals for the Monaka processor. The company aims to achieve twice the energy efficiency of current x86 processors by 2027 while maintaining air cooling capabilities. The processor supports ArmSVE2 with vector lengths up to 2048 bits and is designed to enable artificial intelligence and high-performance computing.
The Monaka processor is scheduled to be released in Fujitsu's fiscal year 2027 (April 2026 to March 2027) and will become a competitor of AMDEPYC and Intel Xeon processors.