Now that three advanced chipmakers have demonstrated CFETS (complementary field-effect transistors), the vision of nearly doubling the transistor density of future processors is beginning to take shape. CFET is a single structure stacking together two types of transistors required for CMOS logic. At this week's IEEE International Electronic Devices Conference in San Francisco, Intel, Samsung and TSMC showed off their progress toward enabling the next step in transistor development.
Chip companies are transitioning from the FinFET device structure used since 2011 to nanosheet or all-gate transistors. These names reflect the basic structure of the transistor. In FinFETs, the gate controls the flow of current through the vertical silicon fins. In nanosheet devices, the fins are cut into a set of ribbons, each surrounded by a gate. CFETs are essentially stacks of taller silicon strips, half for one device and half for the other. Intel engineers explained in the December 2022 issue of IEEE Spectrum magazine that the device stacks two types of transistors - FETs and pFETs - in a single integration process.
Experts predict that CFET will be commercially available in seven to 10 years, but there is still a lot of work to be done before then.
Intel was one of the first three companies to demonstrate CFET, launching an early version at IEDM back in 2020. This time, Intel reported multiple improvements around CFET’s simplest circuit, the inverter. A CMOS inverter sends the same input voltage to the gates of both devices in the stack and produces an output that is the logical inversion of the input.
Marko Radosavljevic, chief engineer of Intel's component research group, told reporters before the meeting: "The inverter is completed on a single fin. At maximum expansion, its size will be 50% of an ordinary CMOS inverter."
Intel's inverter circuit relies on a new way to connect the top and bottom transistors (yellow), as well as a new way to access one of the transistors (gray) from underneath the silicon.
The problem is that squeezing together all the interconnect lines needed to stack two transistors into an inverter circuit negates the area advantage. To keep things compact, Intel is trying to eliminate some of the congestion when connecting to stacked devices. In today's transistors, all connections come from above the device itself. But later this year, Intel will use a technology called backside power transfer that allows interconnects to exist both above and below the silicon surface. With this technique, the bottom transistors are contacted from below instead of above, greatly simplifying the circuit. The resulting inverter has a density quality called contact polypitch (CPP, the minimum distance between the gate of one transistor to the gate of the next), which is 60 nanometers. The CPP of today's 5nm node chips is about 50nm.
In addition, Intel improved the electrical characteristics of the CFET stack by increasing the number of nanosheets per device from two to three, reducing the spacing between two devices from 50 nanometers to 30 nanometers, and using improved geometries to connect various parts of the device.
Using a smaller form factor than Intel's 60nm, Samsung showed results for 48nm and 45nm contact multi-pitch (CPP), although these results were for individual devices rather than complete inverters. While the performance of the smaller of Samsung's two prototype CFETs dropped, it was not significant, and the company's researchers believe manufacturing process optimization will address the issue.
Key to Samsung's success is the ability to electrically isolate the source and drain of stacked pFET and nFET devices. Without adequate isolation, the devices, which Samsung calls three-dimensional stacked field-effect transistors (3DSFETs), can leak current. A key step in achieving this isolation is to replace the etch step involving wet chemicals with a new type of dry etch. This increases the yield of good devices by 80%.
Like Intel, Samsung touches the bottom of the device from below the silicon to save space. However, the Korean chipmaker differs from the American company in using only one nanosheet in each paired device, instead of Intel's three. According to its researchers, increasing the number of nanosheets will improve the performance of CFETs.
Like Samsung, TSMC has successfully achieved the industrially relevant 48nm pitch. What makes its devices unique is a new approach that creates a dielectric layer between the top and bottom devices to maintain isolation between them. Nanosheets are generally formed from alternating layers of silicon and silicon germanium. During the appropriate steps in the process, silicon germanium-specific etching methods remove these materials, freeing up the silicon nanowires. TSMC uses a silicon germanium layer to isolate the two devices, knowing that the silicon germanium layer will etch faster than other silicon germanium layers, so it uses a silicon germanium layer with a particularly high germanium content. This way, the isolation layer can be created in several steps before releasing the silicon nanowires.