Intel's recently officially released Core Ultra Series 3 "Panther Lake-H" mobile processor, its actual wafer photos have been marked by Kurnal Insights, and the internal structure and process distribution of the chip have surfaced. Like the previous generations of Arrow Lake-H and Meteor Lake, Panther Lake-H continues the "disaggregated" design idea, but is closer to Lunar Lake's split plan: an SoC chip manages the CPU main computing cluster and low-power island, NPU and main memory controller, an independent graphics chip is dedicated to the Xe core display computing unit, and the I/O chip integrates various platform I/O components.
Reports indicate that Panther Lake-H’s SoC chiplet is manufactured using Intel’s 18A process. In the Panther Lake-H version for mainstream thin and light notebooks, the graphics chip integrates 4 Xe cores and is built on the Intel 3 process; while the ultra-portable Panther Lake-U version for models without independent graphics and emphasizes core display performance uses a larger graphics chip with 12 Xe cores and switches to TSMC N3E process. The I/O chiplets continue to use TSMC's N6 process node from Arrow Lake.
From the physical structure point of view, Panther Lake-H consists of four chiplets: a base chiplet based on Intel's 22nm process acts as an "interposer" and is responsible for providing high-density micro-interconnection between the chiplets above; computing chiplets, graphics chiplets, and I/O chiplets are stacked on it in sequence. Since the three core chiplets are "connected" in layout but the overall outline is not a regular rectangle, Intel fills in its shape with additional "filler tiles" to ensure that the top of the entire package forms a regular rectangle so that the heat sink can fit evenly.
The computing chiplet is the largest part of the entire processor, measuring approximately 14.32 mm × 8.04 mm, with a total area of approximately 115 square millimeters. 16 CPU cores are integrated in this area, using a combination of 6 Cougar Cove performance cores (P cores) + 8 Darkmont energy-efficient cores (E cores) + 4 low-power island E cores. The main computing cluster consists of 6 P cores and two sets of E core clusters, interconnected through a ring bus (ringbus), and share an 18 MB level three cache (L3).
In terms of cache configuration, each Cougar Cove P core comes with 3 MB of secondary cache (L2), and the two groups of Darkmont E core clusters share 4 MB of L2 (each group of 4 cores is shared). Although the E core in the low-power island is located on the same computing chip, it is not directly connected to the ring bus of the main computing cluster. Instead, it communicates with the main cluster through the on-chip switching fabric. In terms of frequency, the P core has a maximum core frequency of up to 5.10 GHz, and the main E core has a maximum frequency of 3.80 GHz. The low-power island E core has a lower base frequency and is increased to a maximum of 3.70 GHz. It is also a group of 4 cores and shares a 4 MB L2 cache.
In addition to the CPU core, the computing chiplet also integrates the main memory controller, which is front-end equipped with an 8 MB capacity "memory-side cache" to buffer data access to and from the memory. The memory I/O part supports dual-channel DDR5 and LPDDR5X, with data transfer rates up to 9600 MT/s. In addition, this small chip also houses Intel's next-generation NPU 5 neural network unit, including 3 Neural Compute Engines (NCE), each equipped with 1.5 MB cache, for a total of 4.5 MB on-chip work cache for local AI inference tasks. The remaining chip space is likely to be used to lay out key display units such as the media codec engine and display control engine.
For the graphics chiplet part, the report shows a larger version based on TSMC's N3E process, with a physical size of approximately 8.14 mm × 6.78 mm and a total area of approximately 55.18 square millimeters. This chip integrates GPU front-end logic, 12 Xe cores, and 16 MB of L2 cache. The core graphics architecture used by Panther Lake belongs to the Xe3 "Celestial" series, which is Intel's new generation of integrated graphics architecture for high-energy-efficiency graphics and AI workloads.
The I/O chiplet presents a long and narrow strip structure with a size of approximately 12.44 mm × 4 mm and a total area of nearly 49.76 square millimeters, and continues to be manufactured using the TSMC N6 process. This area integrates a PCIe root controller as well as a full Thunderbolt 5/USB4 v2 host router. Official I/O capabilities include: 4 PCIe 5.0 lanes, 8 PCIe 4.0 lanes, 2 Thunderbolt 5 interfaces, and an integrated Wi‑Fi 7 + Bluetooth 5.4 wireless controller.
Overall, while continuing the multi-small chip packaging route, Core Ultra Series 3 "Panther Lake-H" provides a more segmented combination of performance and energy efficiency for the next generation of thin and light notebooks and high-performance mobile platforms through the collaboration of multiple processes such as 18A, Intel 3 and TSMC N3E/N6, as well as the deep integration of CPU, large-core display and NPU. For OEM manufacturers, this more flexible SoC/graphics/I/O split solution is expected to bring more refined specification matching space to notebook product lines at different price points and positioning.