At the recent quarterly financial report corporate briefing, TSMC disclosed relevant plans for 1nm and below process production lines.The company plans to build an A10 wafer fab in Tainan, Taiwan, China. The P1 to P4 fab areas will be used to develop advanced process technologies of 1nm and below. Trial production is expected to start in 2029, with an initial monthly production capacity of 5,000 wafers.
In terms of the Fab 21 factory in Phoenix, Arizona, the future P3, P4, and P5 factories will correspond to the 2nm, A16, and A14 processes respectively. TSMC has also planned 6 factories near the area, with a total of 11 wafer fabs.
Among them, the first advanced packaging factory will start construction in the second half of this year and is targeted to be opened in 2028. It will initially adopt SoIC and CoWoS advanced packaging technologies.
TSMC also confirmed that the next generation of advanced packaging technology is CoPoS, the "panel-based" evolution solution of CoWoS.However, the advancement of this technology is more difficult than expected and takes longer than outside estimates, which makes TSMC's attitude more cautious.
Supply chain stakeholders pointed out that the current bottlenecks faced by CoPoS are mainly focused on issues such as "uniformity" and "warp".
In response to Intel’s recent announcement to join the TeraFab project previously announced by Elon Musk, TSMC also responded.
Wei Zhejia, chairman and CEO of TSMC, said that TSMC and Intel are strong competitors and will never underestimate each other. However, there are no shortcuts in the foundry industry and the basic rules of the game will never change.
