In a new round of competition between AMD and Nvidia in the data center market, the two sides began to "talk" to each other through performance estimates and early testing to build momentum for the upcoming server chip update node. Nvidia has previously claimed that its Vera server processor is ahead of existing AMD Epyc products in multiple loads through benchmark test results strictly controlled by it. AMD's latest internal calculations show that its next-generation "Venice" platform is expected to significantly surpass Vera in rack-level performance.
According to a performance estimate document released by AMD recently, the chip manufacturer believes that the upcoming next-generation server CPU platform will "significantly surpass" Nvidia's latest solution in terms of overall performance indicators. These estimates are directly based on third-party benchmark data that previously favored Nvidia Vera, trying to give the relative advantages of Epyc Venice under the same set of testing methods and assumptions.
AMD's next-generation data center CPU platform Epyc Venice has recently entered mass production and is scheduled to be officially released later this year. Venice is based on the Zen 6 architecture. A single processor can provide up to 256 cores and 512 threads. At the same time, the manufacturing process will be directly jumped from the TSMC 4nm used in the existing Epyc Turin to the 2nm node, skipping the 3nm process in the middle. AMD estimates that compared to Turin, Venice can bring about a 70% improvement in overall performance and energy efficiency, and achieve about a 30% increase in thread density.
When comparing the NVIDIA platform, AMD cited the results of the Vera benchmark test previously completed at NVIDIA headquarters under a series of restrictions. Vera is a server SoC based on the Arm architecture, equipped with 88 cores and 176 threads. In the report, Phoronix called it the "strongest Arm processor" tested so far, and pointed out that it is better than Intel Xeon and existing AMD Epyc products under most workloads. However, this batch of tests has been approved by Nvidia and has strict control over the test environment and configuration.
On this basis, AMD conducted rack-level calculations based on unified assumptions, including comparing factors such as the number of single CPU cores, node power consumption, the number of nodes that can be deployed per rack, and the 100-kilowatt rack power budget. Under this model, AMD believes that the per-rack performance of Epyc Venice can reach 3.3 times that of Vera; at the same time, the existing 192-core Epyc 9965 Turin and 128-core Intel Xeon 6980P GNR-AP are also estimated to reach approximately 2.37 times and 1.46 times the output capabilities of Vera respectively under the same conditions.
In addition to rack-level throughput, AMD also pointed to per-core performance, saying that under the same benchmark system, its 64-core Venice processor can lead Vera in per-core performance by about 27%, while the 96-core version can achieve an advantage of about 11%. Since both products are positioned as server platforms for AI workloads, AMD believes that on the premise that per-core performance and core count are simultaneously improved, Venice is expected to provide more attractive computing power density within the same rack power consumption constraints when facing "agentic" AI deployment scenarios. Of course, until independent testing institutions obtain mass-produced chips and complete public comparisons, these gaps will still remain at the level of theoretical estimates given by manufacturers.
While preheating for Venice, AMD also began to "lay the groundwork" for the next generation architecture. According to its roadmap, "Verano" will be AMD's first CPU product designed specifically for AI infrastructure and will be the first to adopt the Zen 7 architecture. Supply chain sources pointed out that Zen 7 is expected to be introduced into TSMC's A14 process node. This approximately 1.4nm-level process is regarded as a key step for AMD to enter the "Am-level era" and is expected to continue to bring further improvements in performance and energy efficiency based on 2nm. However, AMD has not yet given official confirmation on these details.