The research team of the Korea Advanced Institute of Science and Technology (KAIST) successfully developed ultra-efficient liquid cooling technology built into the chip.This technology can still control the chip core temperature within 100°C under extreme heating conditions of 2000W/cm², and the cooling coefficient of performance (COP) reaches 106000.It is ten times the world's best record (about 10,000) published in the journal "Nature" in 2020, and only requires 1/10 of the pumping power consumption of traditional top cooling solutions.
The core innovation of this technology is to embed micron-level liquid-cooled microchannels with a diameter far smaller than a human hair directly into the silicon semiconductor chip to achieve an integrated integration of the heat dissipation structure and the chip body.
The key to truly widening the gap lies in the redesign of the manifold microchannel (MMC) structure. In traditional microchannel heat dissipation technology, the coolant needs to flow through the entire microchannel of the chip from one end to the other to complete heat exchange. An overly long flow path greatly increases resistance, requires higher pumping power, high energy consumption and uneven heat dissipation.
In this regard, KAIST designed a new manifold shunt structure to reconstruct the circulation logic of the coolant. The coolant is evenly distributed through multiple sets of distributed inlet channels. After heat exchange is completed, the coolant is uniformly recycled through multiple outlet channels to form a short-path, distributed heat dissipation circulation network.
Under this design, the flow distance of the coolant in a single flow channel is greatly shortened, and the fluid resistance and pumping pressure are significantly reduced. At the same time, the coolant evenly covers the entire chip to prevent local overheating.
Focusing on core parameters such as the width, height, arrangement quantity, layout method, and coolant flow rate of microchannels, the team built a multi-fidelity optimization framework. It first screened a large number of basic design plans through a one-dimensional model to quickly eliminate inefficient structures, and then relied on high-precision simulation to fine-tune high-quality solutions.
This layered R&D model breaks through the bottleneck of traditional heat dissipation design, which is limited by computing power and cannot traverse massive solutions, and simultaneously achieves collaborative optimization of the three core indicators of heat dissipation performance, fluid pressure drop, and chip temperature uniformity.
In terms of practicality,The entire solution does not require complex processes such as phase change refrigeration or nano-surface modification, nor does it rely on high-priced special heat dissipation materials such as diamond. It only uses ordinary normal-temperature water as the cooling medium, significantly reducing construction and operation and maintenance costs.
The preparation process temperature of chip-integrated microchannels is lower than 350°C, which is fully compatible with the current mainstream semiconductor mass production manufacturing process. There is no need to carry out large-scale transformation of existing production lines or add expensive equipment.
Its application scenarios cover many high-end fields such as AI acceleration chips, high-performance computing systems, three-dimensional semiconductor packaging, power electronic devices, and military precision electronic equipment.