Ming-Chi Kuo recently interpreted TSMC’s advanced packaging technology and pointed out that glass core substrates are a necessary condition for the manufacturing of next-generation AI chips, rather than an optional optimization solution. This technology originated from TSMC's technical speech at Japan's JPCA Show on June 11. TSMC has teamed up with IFI and Innolux to develop a glass core substrate. It adopts a three-layer structure design, with the glass core sandwiched between two layers of ABF laminates.
The thinner thickness of the glass substrate greatly shortens the vertical conduction path through the through-glass hole. The conduction resistance and loop inductance decrease simultaneously, and the power integrity is significantly improved, providing a more stable power supply system for the chip.
Ming-Chi Kuo distinguished the positioning differences between the two technologies in the CoPoS system. CoP mainly affects production efficiency and cost and is an optimization option, while OS directly determines whether the chip can be successfully manufactured and is a must-have core technology.
The current test substrate specification is 250 x 250 mm. The ABF laminate uses Ajinomoto GL107 hybrid material with a number of layers of 24 to 28. Through-glass vias are the core technical barrier and are jointly mastered by TSMC and Innolux.
Although the unit price of the glass substrate is much higher than that of the traditional ABF substrate, its cost only accounts for a low single-digit percentage of the overall bill of materials of the AI chip. However, it can significantly reduce the yield loss caused by poor packaging, and the overall economic benefits are significant.
Nvidia and two other American chip giants have shown strong interest in this technology. Improved power integrity can be directly converted into improved AI computing power to meet the performance needs of the next generation of high-end chips.
TSMC aims to start mass production of glass substrates from the fourth quarter of 2028 to the first quarter of 2029 to match the iterative pace of next-generation AI chips from giants such as Nvidia. The industry chain is currently accelerating verification.
