Abstract:
Intel recently announced more technical details of its next-generation Xeon 7 server processor platform Diamond Rapids (codenamed DMR) at the Hot Chips conference. The platform was originally planned to be launched in 2026, with a maximum configuration of 192 cores and 16 memory channels, but it has been confirmed to be postponed to 2027. At the same time, Intel has further increased the core number of its flagship model to 256 performance cores, directly benchmarking AMD's sixth-generation EPYC Venice series, which also has a maximum of 256 cores.
Different from previous products targeting the broader server market, Diamond Rapids will focus on high-performance computing. This platform completely cancels hyper-threading technology, which is often referred to as simultaneous multi-threading (SMT) in the industry, and only provides high-end AP versions for the high-core market. The originally planned 8-channel Diamond Rapids-SP product has been cancelled. Therefore, DMR will not cover all levels of AMD's product line, but will focus on competing for the top HPC market.
Intel's subsequent Coral Rapids products are expected to reintroduce hyper-threading technology and may bring a new generation of SP series processors. However, in terms of architectural complexity, Diamond Rapids is still one of Intel's most sophisticated Xeon processors to date. To a certain extent, its design idea is reminiscent of the modular chiplet route introduced by AMD with EPYC Rome in 2019: splitting computing, I/O and memory functions, and then flexibly combining them according to different product needs. After exploring several generations of products, Intel seems to have finally found a multi-core integration method that is more suitable for itself.
A single Diamond Rapids processor can be composed of up to 22 cores, and can be increased or decreased according to the needs of computing power, cache capacity and memory configuration. These cores are mainly divided into three categories: up to 16 computing cores manufactured using the Intel 18A-P process, 4 computing building block basic cores manufactured using the Intel 3-T process, and 2 scalable Fabric Hub cores based on the Intel 3 process, which are responsible for connecting various parts of the system.
Among them, 18A-P is an improved version of Intel's 18A process and belongs to the 2nm level process technology. Intel claims that under the same performance, this process can reduce power consumption by 18%; under the same power consumption, it can bring about a performance improvement of up to 9%. In addition to process gains, Diamond Rapids will also adopt a new performance core microarchitecture, so actual performance will also be affected by core IPC improvements.
Each computing core integrates up to 16 cores and their corresponding L2 cache. Up to four of these computing cores will be stacked on top of a computing building block base core using Foveros 3D direct hybrid bonding technology. The base chip integrates L3 cache: each computing building block provides 320MB of L3 cache, and the top Diamond Rapids model has a total L3 cache capacity of up to 1.28GB.
Intel does not use EMIB embedded multi-core interconnect bridges to connect computing modules with I/O and memory modules. Instead, it adopts a packaging interconnection solution closer to the UCIe-S style, which transmits data through an organic packaging substrate instead of a silicon bridge. Intel calls this new die architecture a "fan-out interconnect architecture."
Two scalable Fabric Hub chips integrate the memory controller and I/O interface. Their design concept is similar to the I/O Die in AMD's recent generations of EPYC server processors. By replicating such dies, Intel can expand memory channels and interconnect capabilities. Two Fabric Hubs can provide a total of up to 16 DDR5 memory channels. The standard DDR5 memory rate can reach up to 8000MT/s, and when using MRDIMM, it can reach 12800MT/s.
In terms of expanded connectivity, Diamond Rapids supports up to 128 PCIe 6.0, CXL 3 or UPI 3 lanes, in addition to 8 PCIe 4.0 lanes, which may be used for auxiliary I/O devices such as onboard network, USB or baseboard management controllers.
This design also reflects Intel's adjustments to memory access methods. Previous Granite Rapids-APs presented themselves as three non-uniform memory access (NUMA) nodes by default, while Xeon 7 Diamond Rapids hopes to offer a unified memory access (UMA) architecture. Due to the new packaging interconnection method, the computing building block can directly communicate with two Fabric Hubs, avoiding the problem of accessing different I/O modules through additional jumps. Intel believes that this design can not only help realize UMA but also control the cost of advanced packaging.
However, there are still many key parameters of the DMR platform that have not yet been announced. Intel has not stated the maximum frequency of the core, nor has it disclosed the IPC improvement of the new performance core compared to Granite Rapids. Specific details of the cache level are also limited, and currently only the L3 cache capacity can be confirmed to be very considerable.
In terms of instruction set, Diamond Rapids will support the updated AMX matrix extension instructions and add FP8 support to improve the efficiency of the CPU when executing machine learning tasks. The processor will also be one of the first products to fully support AVX 10.2. AVX 10.2 aims to improve some limitations of Intel's early AVX-512 implementation and is of great significance for high-performance computing and supercomputing applications.
While UMA is expected to become the default configuration, NUMA support remains critical for HPC workloads that require splitting large numbers of cores into smaller resource domains. Intel has not yet detailed how DMR will implement NUMA partitioning, but from an architectural point of view, the processor can theoretically be divided into two, four or even more sub-NUMA clusters. Whether to open this capability may mainly depend on BIOS settings.
Product stratification is another unsolved problem. It is currently known that Intel will launch 256-core and 192-core versions, but it is not clear to what extent the core number will be reduced. In theory, Intel can tailor the product to a version with only one computing building block and a 16-core computing core; but a more realistic judgment is that the minimum configuration of Diamond Rapids may fall between 64 cores and 128 cores.
Judging from the published specifications, Diamond Rapids is expected to become Intel's most competitive generation of high-end Xeon in recent years. AMD's Venice EPYC and Intel's DMR will both provide up to 256 cores, 16 memory channels, more than 1GB of L3 cache, and similar interconnect capabilities; the thermal design power consumption of both sides' flagship products is also expected to be around 600W.
Intel's obvious shortcoming is that it does not have hyper-threading technology. In some workloads that are highly dependent on the number of threads, AMD may still achieve a double-digit performance advantage with SMT even if the core performance of both parties is similar. But in the HPC world, hyper-threading doesn't always bring benefits. For example, the HPL benchmark, used to rank supercomputers around the world, typically does not necessarily benefit from hyper-threading. Arm has even stated before that synchronized multi-threading may do more harm than good in some scenarios.
This also gives Diamond Rapids the possibility of being positioned by Intel as a low-latency AI agent sandbox processor, such as a Python code execution environment that hosts AI generation, or an isolation container for compiling and running C and Rust code. But even so, there is a high probability that DMR will not become Intel's high-volume product, especially in the context of Nvidia's promotion of self-developed Vera CPU as the preferred host-side processor for AI systems.
Ultimately, Diamond Rapids' market performance will still depend on price and value for money. When AMD launched EPYC Rome, it might not be able to overwhelm Intel in single-core performance, but it provided a more attractive unit cost value with its higher core count, richer I/O and greater memory expansion capabilities. If Intel can deliver more cores at a lower price, Xeon 7 may still be competitive for certain customers even if AMD has better absolute performance.
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