The trend is like an undercurrent, coming rapidly, and the industry leaders are also in a hurry. When the process miniaturization game of semiconductor processing comes to an end, advanced packaging has gradually become the winner in the chip industry. At the beginning of the year, no one could have imagined that the semiconductor industry would be in such a state of chaos this year. This year, when the entire chip industry is suffering from destocking, NVIDIA's AI chips are hard to find. Domestic Internet giants personally flew to NVIDIA's headquarters in California, just to get a few more A800 and H800 chips.
01
The trend is like an undercurrent: Leader Huang went into battle to urge orders, TSMC hurriedly expanded production
This is not because Master Huang has a rare commodity, but because the entire AI chip industry is suffering from insufficient production capacity of TSMC.
On May 27, Leader Huang was ostensibly going to National Taiwan University to deliver a graduation speech. Although the chicken soup for the soul given by the entrepreneurial tycoon to the young students is delicious, in fact, urging TSMC to expand production is one of the core purposes of Huang's trip. It is understood that TSMC is already coordinating to increase production capacity and is expected to reach a production capacity of 200,000 pieces by the end of 2024. CEO Wei Zhejia at the TSMC shareholder meeting said that it will increase efforts to expand CoWoS production capacity at the Longtan factory, and the Zhunan AP6 factory will also join in support.
Picture: Huang Renxun attended the graduation ceremony of National Taiwan University and delivered a speech
Isn’t it said that chip foundry production capacity is overcapacity? Why does Lao Huang need to personally go to TSMC to supervise the war? Contrary to popular belief, what is tight this time is not the wafer foundry of advanced processes such as TSMC's 7nm and 5nm, but the advanced packaging that was not taken seriously before and has become the shortest link in the entire industry chain.
In the semiconductor industry division of labor, packaging has always been at the bottom of the contempt chain. With low added value and high capital expenditure, chip companies try to avoid it.
This shortage of AI chips has brought CoWoS, one of the representatives of advanced packaging technology, into the spotlight for the first time. This previously unpopular term has become a household name. The industry is even exaggerated to the point that it can directly track the production capacity of advanced packaging CoWoS to predict Nvidia's next quarter's performance, and then buy call options crazily during Nvidia's earnings season.
If we make a logical deduction from top to bottom, it is as follows: industry giants are competing for an AI arms race -> the AI arms race requires a large number of AI chips -> AI chips require TSMC foundry -> TSMC foundry is constrained by advanced packaging CoWoS production capacity.
It is no exaggeration to say that advanced packaging has become a phoenix overnight and has become the biggest bottleneck restricting the development of the TMT industry.
Even though TSMC, as the unshakable big brother in semiconductor manufacturing, is still leading the way in advanced packaging, it is obviously not prepared for the rapid development of this trend. Under the urging of customers, it can only urgently urge equipment manufacturers to passively increase CoWoS production capacity.
This is also the first time that everyone has to face up to the packaging industry.
Figure: Semiconductor industry chain; Zhongtai Securities
02
When traditional thinking comes to an end
The most direct way to improve chip performance is to increase the number of transistors as much as possible, which is no different from increasing the battery life of electric vehicles by stacking more battery packs. Therefore, for the development of the semiconductor industry, the traditional idea of advanced chip research and development has always been to "make a fuss about transistors." Simply put, it is to expand the chip area while shrinking the process.
Among them, the purpose of process shrinkage is to put more transistors per unit area, which is what we often hear about 14nm, 7nm, 5nm, and 3nm. In this way, the transistors can be made smaller and smaller, and naturally more transistors can be stacked per unit area. The other way is to expand the area, which is to make the chip larger as much as possible under the premise of a given process.
It can be said that in the past few decades, the logic chips of computers and mobile phones we have relied on this method to extend their lives. As this method has developed to this day, it has inevitably hit two major limitations.
Limitation 1: The marginal benefits of process shrinkage are getting smaller and smaller.
In fact, since 28nm, the cost-effectiveness of pursuing more advanced processes in chip design has become increasingly lower. According to data disclosed in VeriSilicon's prospectus, the unit area cost of chips increased rapidly after 14/16nm, and Moore's Law continued to slow down. As the process evolves from 28nm to 5nm, single R&D investment has also increased sharply from US$50 million to more than US$500 million.
Advanced processes have become a money-burning competition, so only a few companies such as Apple, Nvidia, Samsung, AMD, Intel, MediaTek, Tesla, and Huawei are making the most advanced chips. At the beginning of the year, OPPO had no choice but to disband its Zheku team, which is the best example of the high threshold for developing advanced chips.
Precisely because the advanced input-output ratio is not necessarily appropriate, many chips stay after 28nm and no longer blindly pursue advanced processes.
Figure: Chip design costs of different process nodes in various application periods (unit: million US dollars); Source: VeriSilicon Prospectus
Limitation 2: The yield rate of large-size chips is getting lower and lower.
In addition to pursuing advanced processes to increase transistor density, another method is to make the chip larger. It is said that great efforts can produce miracles. However, this simple method has basically come to an end.
Still taking Nvidia’s AI chip as an example. Compared with traditional chips, AI chips have larger areas in order to achieve ultimate performance. The size of NVIDIA's AI bare chips usually exceeds 800mm2, which is several times larger than ordinary mobile phone main control chips. The direct problem caused by too large a chip is that the production yield rate decreases rapidly.
There is a Bose-Einstein model in the industry for judging process manufacturing yield: yield = 1/(1+chip area*defect density)n. It is not difficult to see from this formula that the larger the area of a single chip, the lower the yield rate will be.
Some people will naturally say that it doesn’t matter if the yield rate is low, as long as we make a few more, it will be fine. This is obviously due to insufficient understanding of industrial production. NVIDIA AI chips are now sold for more than US$10,000 per chip, and no one can afford the losses caused by low yield rates.
According to model estimates, the yield rate of medium and large chips of 150mm² is about 80%, while the yield rate of ultra-large chips of 700mm² and above will plummet to 30%. Moreover, according to industry insiders, due to the size limitations of photolithography masks, the area of a single chip generally does not exceed 800mm2, so Nvidia's AI chips are actually approaching the upper limit of area.
When the methods to promote the advancement of advanced chips begin to face unprecedented challenges, the industry must find new ways to survive.
03
Bump into the future and uncover the mystery of advanced packaging
Although the packaging industry is not as eye-catching as chip design and wafer foundry, thanks to the rapid development of chip types, the scale of the global chip packaging industry is also considerable. The market size will exceed US$80 billion in 2022. It is an industry that is difficult to ignore, but it has always been labeled as cyclical.
Returning to the industry, semiconductor packaging is a back-end process of the semiconductor manufacturing process. It is designed to better realize electrical connections between chips and other electronic components. Someone in the industry once made a metaphor that the chip is equivalent to the cerebral cortex, and packaging is like the skull of the brain. Therefore, in the long history of semiconductors, packaging has only played a supporting role, and the market attention has not been high. It's just advanced packaging that brought the packaging industry to the forefront for the first time.
On another level, the technological development of the packaging industry is not slow, and it is not a so-called "purely cyclical" industry.
In the past 70 years, the packaging industry has experienced at least four major technological changes. Especially since the 2010s, the industry has gradually entered a new development stage of advanced packaging (in 2010, Mr. Jiang Shangyi proposed a method of connecting multiple chips through semiconductor companies, which is different from traditional packaging and is defined as advanced packaging). Since then, new concepts have begun to emerge one after another, such as FC, SiP, 2.5D packaging, 3D packaging, FO, RDL, TSV, etc.
Of course, this also makes researchers who study advanced packaging in 2023 suddenly overwhelmed by so many unfamiliar vocabulary, which is really overwhelming.
Figure: History of packaging technology development
Understanding advanced packaging is actually not complicated. Following the idea mentioned before, since it is increasingly unfeasible to simply expand the area of a single chip and reduce the manufacturing process, can we split the single chip that was originally supposed to be very large into different functional modules, and then use a certain process to make small chips with excellent performance? Finally, these small chips are put together to form a "big chip" to achieve the effect of "three stooges compared to Zhuge Liang".
This is the bottom-level principle of advanced packaging, which greatly reduces the difficulty by breaking it into parts. If different chips are made of the same materials and then packaged together, this is called heterogeneous integration in the industry; if even some chips are made of different materials and then packaged together, this is called heterogeneous integration in the industry.
In order to realize the above ideas, the industry relies on the development of new processes to turn this idea into reality, such as TSV technology (ThroughSiliconVia, through-silicon via technology) and RDL (redistribution technology) that realize the connection between silicon wafers.
Take 3D packaging as an example. If the upper and lower stacks are of the same type of chip, TSV can usually directly complete the electrical interconnection function. If the upper and lower stacks are different types of chips, the IOs of the upper and lower chips need to be aligned through the RDL rewiring layer to complete the electrical interconnection.
Still going back to NVIDIA's AI chips, as a representative solution for advanced packaging, although CoWoS was developed by TSMC and Xilinx 10 years ago, it was eventually carried forward on NVIDIA's AI chips.
NVDIA's current main products, the A and H series, both use TSMC CoWoS2.5D packaging. Taking A100 as an example, the main chip A100 is a single-chip architecture using a 7nm process, and is equipped with Hynix's HBM. High-speed interconnection between these two most important chips is achieved through CoWoS.
Figure: CoWoS packaging solution provided by TSMC to Nvidia.
Therefore, in the past, the industry was still doubtful about advanced packaging (packaging factories did not invest heavily, but wafer factory TSMC suddenly emerged), but NVIDIA's hot-selling AI chips officially announced that advanced packaging is becoming the winner of semiconductors.
Industry leading players also realize that advanced packaging will play an increasingly important role as Moore's Law approaches the physical limit, so they are urgently catching up on advanced packaging.
For example, toothpaste manufacturer Intel focuses on two advanced packaging solutions:
1) 2.5D packaging EMIB, focusing on low cost; 2) Foveros3D face-to-face chip stacking packaging technology, focusing on high performance.
According to reports, the 14th generation CPU Meteor Lake that Intel plans to launch this year will introduce a Tile-like chiplet design for the first time, integrating four independent modules of CPU, GPU, IO and SoC, and using Foveros packaging technology.
Samsung currently has four advanced packaging solutions, including I-Cube, X-Cube, R-Cube, and H-Cube. The technical principles are similar, so I won’t go into details.
Leaving aside the technical details, in fact, the advanced packaging of different manufacturers are similar to TSMC, but they have been circumvented to a certain extent in order to distinguish and avoid patent disputes. There is no essential difference between different names. More importantly, after the giants began to realize the importance of advanced packaging, they chose to join if they could not beat them.
According to the summary of Minsheng Securities, we can see that in the future, products relying on advanced packaging will penetrate into servers, mobile phones, AI, wearables and graphic displays, basically involving all aspects of life, and their importance will increase day by day.
Figure: Representative solutions for global advanced packaging; Source: Minsheng Securities.
04
What does one more meaning mean to the domestic industrial chain?
Naturally, everyone has to ask, how is our country doing with such an important trend?
First of all, we need to clarify a potential misunderstanding. Although the development of the domestic semiconductor industry is lagging behind, the packaging industry chain has relatively low technical barriers and relatively early development, so its global competitiveness is still remarkable.
According to statistics, among the top ten packaging companies in the world, 3 are from mainland China, 5 are from Taiwan, and 1 is from the United States. Among them, Changdian Technology, Tongfu Microelectronics and Huatian Technology are known as the three domestic packaging and testing giants, and they all rank among the top ten in the world. Moreover, the business layout of these three packaging factories is very global, with overseas revenue accounting for more than 50%. Taking Tongfu Microelectronics as an example, most of AMD's packaging is completed by Tongfu Microelectronics. Therefore, it is not an exaggeration to say that domestic packaging factories have global competitiveness.
Figure: Ranking of the world’s major packaging and testing plants; Data source: China International Finance Securities.
It has to be said that although we are not lagging behind in packaging, advanced packaging is indeed a step behind.
Let’s talk about data. In the entire advanced packaging field, ASE’s share reaches 26%, followed by TSMC and Amkor, while the market share of the highest-ranking domestically produced Changdian Technology is only 8%. If it further rises to the most cutting-edge advanced packaging, then the domestic presence will be even weaker. As evidence, the CoWoS required by Nvidia, the presence of the industry chain in mainland China is equal to 0.
With this global wave of advanced packaging, domestic packaging factories have also begun to turn in time. According to industry research information:
●Changdian Technology has laid out its plans in TSV-less, RDL and other technologies. It has launched XDFOI technology solutions and achieved mass production and shipment of 4nm node chiplet products for international customers.
●Tongfu Microelectronics has launched VISionS, an advanced packaging platform that integrates 2.5D, 3D, MCM-Chiplet and other technologies. It currently has 7nm Chiplet mass production capabilities and continues to strengthen cooperation with leading manufacturers such as AMD. It is expected to play an important role in AMD's MI300, which is about to be mass-produced;
●Huatian Technology launches the latest advanced packaging technology platform - 3DMatrix, consisting of TSV, eSiFo, and 3DSiP.
Putting aside these packaging plants, what significance does advanced packaging have to the domestic semiconductor industry chain?
In fact, advanced packaging is not only a necessary process for the development of AI and other chips, but also an important "corner" for achieving breakthroughs in the country. This is because advanced packaging is the cornerstone process for realizing chiplet technology.
Many people confuse chiplets with advanced packaging. By definition, chiplets are divided into multiple identical or different small chips. These small chips can be manufactured using the same or different process nodes, and then integrated at the package level through cross-chip interconnection and packaging technology to reduce costs and achieve higher integration.
So chiplet is just a design concept, and one of the most important processes to realize this design concept is advanced packaging. It's just that this concept is of greater significance to the development of domestic chips.
Under the overseas blockade, if we only rely on the domestic industrial chain, the theoretical limit of what our chip manufacturing process can achieve is about 7nm, which is still more than two generations behind the overseas 3nm. To further make up for the generation gap, it is necessary to stack multiple small chips, which may be able to produce higher-performance products.
To put it simply, we can use chiplets to achieve blockade breakthroughs and even change lanes to overtake.
According to the law of industry development, advanced packaging is increasingly becoming the winner of semiconductor competition, and together with advanced manufacturing processes, it has become a necessary process for advanced chips; for the domestic chain, advanced packaging is the only way to achieve overtaking in corners. To sum up, the domestic development of advanced packaging is actually more urgent. When the revolution takes a new direction, comrades need to work harder.
access:
Jingdong Mall