The JEDEC Solid State Technology Association recently announced that its JC-40 and JC-45 committees responsible for the formulation of logic and DRAM module standards have made a number of important developments in the field of DDR5 MRDIMM (Multiplexed Rank Memory Modules), including the official release of a new generation of DDR5 multiplexed rank data buffer standards, advancement of the formulation of multiplexed rank clock register driver standards, and accelerated improvement of DDR5 MRDIMM Gen 2 and Gen 3 roadmaps for higher bandwidths.
Among the published standards, JEDEC officially announced the JESD82-552 "DDR5MDB02 Multiplexed Rank Data Buffer" specification, which has been open for download on the official website. This standard defines a new generation of data buffering functional design for multiplexed rank DIMM architecture, aiming to maintain stable and reliable operating characteristics even as module bandwidth continues to increase. By introducing more advanced buffering and control logic on the data path, the DDR5 MDB solution provides stronger scalability and signal quality assurance for high-performance memory subsystems.
The upcoming JESD82-542 "DDR5MRCD02 Multiplexed Rank Clock Register Driver" standard has also entered the final stage and is expected to be officially announced soon. This standard is oriented to DDR5 MRDIMM modules, focusing on strengthening the integrity and timing control capabilities of clock and control signals to match the data buffering specifications in JESD82-552, and overall further improve the reliability of MRDIMM products in high-frequency and high-bandwidth scenarios.
In terms of module specification roadmap, the JC-45 committee is stepping up its efforts to complete the formulation of the MRDIMM Gen 2 standard. The goal is to meet the continuous increase in bandwidth of new generation computing platforms while taking into account the energy efficiency and system efficiency requirements at the overall machine level. At the same time, the committee is also advancing the second-generation DDR5 MRDIMM Gen 2 original PCB (raw card) design. The target data rate of this batch design is 12,800 MT/s, which reflects JEDEC’s hope to provide higher data transfer rates and scalable memory solutions for data-intensive application scenarios through standardization work. While the Gen 2 standard is nearing completion, JC-45 has also begun planning the MRDIMM Gen 3 standard, and the relevant underlying memory interface logic is also nearing the finalization stage.
JEDEC will also hold special forums for mobile/client/edge, and server/cloud computing/AI fields in San Jose in May this year to conduct in-depth discussions around next-generation memory standards and system design, including DDR5. Attendees will have the opportunity to learn about the latest specification progress and industry application trends of cutting-edge technologies such as MRDIMM. The relevant agenda and registration information have been published on the JEDEC official website.
Mian Quddus, chairman of the JEDEC JC-45 Committee and chairman of the association's board of directors, said that this series of coordinated standards work reflects JEDEC's continued role as an industry "aligner" in the field of high-performance memory standards. By creating interoperable unified specifications, it can meet the growing performance and bandwidth requirements of AI, cloud computing and enterprise-level workloads on memory subsystems. Source: JEDEC official press release.