According to reports from industry media citing sources such as South Korea's ETNews, Intel is planning to adjust and upgrade its process roadmap in response to the 1.4-nanometer chip manufacturing technology that TSMC and Samsung Electronics will launch in the next few years, and is considering launching an improved version of the process called "14A2" (14A Gen2) based on its standard 14A process.

According to the current plans of all parties, TSMC is expected to bring its A14 fab online as soon as next year, while Samsung Electronics aims to achieve mass production of its 1.4nm process in 2029. Facing the pressure of competitors, Intel originally planned to launch its breakthrough 14A technology within the next year and use this to attract external foundry customers to reshape its wafer foundry business. The 14A2 reported this time is an important result of technical refinement and maturity improvement of the standard 14A process.
In terms of technical architecture, the standard 14A process uses "PowerDirect" technology, which is the back power supply network (BSPDN). However, the latest industry news shows that Intel is considering introducing a disruptive "Dual Side" power supply architecture in the subsequent 14A2 process, which means that the chip will use both the front and back sides for power supply. In addition, the M0 metal pitch (Pitch) of the basic 14A process will be reduced to 28 nanometers, while the new 14A2 process plans to further compress the metal pitch to 21 nanometers through improved technologies such as double pattern exposure (Double Patterning), thereby achieving higher transistor density. Given that the basic version 14A has previously been announced to bring about a 30% increase in transistor density, the density gain of 14A2 will undoubtedly be more advantageous.

Although this upgrade can significantly increase the utilization rate of expensive equipment such as high-diameter high-numerical aperture extreme ultraviolet (High-NA EUV) lithography machines and increase the profitability of a single machine, the ultra-fine pitch of 21 nanometers also brings technical complications, such as a substantial increase in resistance. At the same time, existing nano-through silicon vias (nTSVs) designs are unable to directly withstand such high-density power loads. In order to overcome this bottleneck, Intel is rumored to have adopted a composite structure that continues to use the back power supply network (BSPDN) as the main power supply source of the core, but at the same time allocates part of the power distribution to the front metal layer to maintain the stability of the overall circuit.
Currently, TSMC is facing a situation where its order volume is almost saturated, which has also prompted many chip design manufacturers to start looking at other foundries such as Intel and Samsung. Intel is currently confident of regaining its leadership position in semiconductor manufacturing, but as a latecomer to the foundry market, it still needs to prove its ability to mass-produce to external customers. Judging from the current market structure, Intel's subsequent 18A-P, 14A and newly exposed 14A2 processes have become the focus of the entire semiconductor industry.