On September 13, 2023, at Apple's autumn new product launch conference, the world's first 3nm chip A17Pro was launched together with the iPhone15Pro series, which is still produced by Apple's old friend TSMC. Before the release of this chip, everyone had high hopes for it. Compared with small nodes like 4nm, 3nm is another important process iteration after 5nm. Looking back on past history, every major upgrade of the process will bring about another substantial improvement in chip performance, and the same should be true for 3nm.


But an accident happened. The improvement of this supposedly powerful A17Pro chip was not as great as everyone imagined. Instead, the heating problem of iPhone15Pro turned Apple into a "dragon fruit".

So, should TSMC be responsible for the heat?

Heat dissipation that is irresistible

Someone soon came to support TSMC. Tianfeng International analyst Ming-Chi Kuo published an article today explaining the current overheating problem of Apple's iPhone 15 Pro mobile phone and stated that it "has nothing to do with TSMC's 3nm process."

Ming-Chi Kuo said that the overheating problem of the iPhone 15 Pro series has nothing to do with TSMC's 3nm process. It is probably mainly due to the compromise in the heat dissipation system design to make it lighter, such as a smaller heat dissipation area and the use of titanium alloy that affects the heat dissipation effect.

Of course, there is nothing wrong with this. According to the current disassembly, the iPhone 15 Pro still uses a double-layer motherboard, with a ROM chip on the back and a baseband chip in front. They are all chips that generate a lot of heat. Putting them together is like letting the A17 Pro stay next to a campfire. If the load is large, the fire will become bigger. Not only will the processor run at a reduced frequency, but the user will soon feel the heat of the phone.


In addition, the titanium alloy frame that Apple has promoted for a long time at this press conference actually exacerbates the problem of poor heat dissipation of the iPhone in disguise. The thermal conductivity of titanium is λ = 15.24W/(m.K), which is about 1/4 of nickel, 1/5 of iron, and 1/14 of aluminum. The thermal conductivity of this titanium alloy is about 50% lower than that of pure titanium. This means that although the iPhone 15 Pro is lighter, the heat dissipation is not as good as the aluminum alloy frame of the iPhone 15 and the stainless steel frame of the iPhone 14 Pro.

However, Ming-Chi Kuo’s words are not comprehensive. According to domestic Geek Bay tests, the battery life of iPhone 15 Pro and iPhone 15 Pro Max has regressed compared to the previous generation, dropping by about dozens of minutes. On the basis of a slight increase in battery capacity, the battery life has been shortened. In addition to the performance scheduling of the processor itself, the problem may still lie in the energy efficiency of the A17 Pro itself.

According to Techinsights' chip teardown, compared with A16, the area of each performance core and efficiency core of A17Pro is reduced by 20%, the area of each GPU core is increased by 5%, and the overall GPU core is increased by 20%. Due to the advancement of process technology, the overall area of the A17Pro chip has shrunk slightly, but the number of transistors has reached a new high of 19 billion, an increase of nearly 20% compared to the previous generation's 16 billion transistors. The ability to complete such a large upgrade is indispensable to TSMC's 3nm process.


However, according to Apple’s official announcement, the overall performance of the A17Pro’s CPU is only about 10% higher than the previous generation. The 20% improvement in the GPU is largely due to the change from 5 cores to 6 cores. Only the NPU has the largest improvement. The computing power has been upgraded from 17TOPS to 35TOPS. It is not difficult to guess that its actual scale has become much larger. In addition, the addition of the new USB3 controller, these are the main upgrade points of the A17Pro, and it has not completed the significant leap that many people expected.

When A17Pro lost its mythical halo, TSMC's 3nm was also questioned.

FinFET is exhausted

Why did TSMC, which was still going smoothly at 4nm, turn over when it came to 3nm?

At 5nm, both TSMC and Samsung use FinFET (Fin Field Effect Transistor) technology to control the current flowing through the transistor. This technology can control the passage of electrons from "three sides" (as shown below). If the electrons are not well controlled and run around, it will cause leakage, which will in turn increase the temperature of the phone.

In order to better control the current, the two semiconductor giants have developed a technology to control the passage of electrons from "all sides", called GAA (Gate-All-Around), to further prevent leakage. However, at the 3nm node, TSMC chose to continue using the FinFET process and did not convert to GAA until 2nm. Samsung was the first to introduce GAA at 3nm. Although it has not yet been mass-produced, it is expected to provide better power consumption and density than FinFET.

In 2011, Intel applied 22nm FinFET technology to its IvyBridge microarchitecture processor for the first time. In 2014, TSMC and Samsung introduced FinFET technology into the 16/14nm process for the first time. In the following years, FinFET became a popular technology for many wafer factories. Traditional planar processes could not meet the needs of advanced processes, and Moore's Law was once again continued.

But within a few years, below the 7nm process, the problem of static leakage became more and more serious, and the power consumption and performance dividends of the original process evolution gradually disappeared. It has become a consensus that FinFET cannot meet the needs of 3nm and more advanced processes. When to introduce GAA has become the focus of many people. Intel and TSMC chose to continue to use FinFET at 3nm, while Samsung, which is at a competitive disadvantage, made up its mind to introduce GAA technology at 3nm in an effort to win more customers.

At the TSMC Technology Seminar in August 2020, TSMC said that it has made a major update to its FinFET technology. N3, or 3nm, will use an expanded and improved version of FinFET, with performance gains of up to 50% and power consumption reductions of up to 3 0%, the density gain is 1.7 times higher than that of N5. However, it should be noted that this comparison is only a comparison between the first generation N3 and N5. After N5 was upgraded to the latest N4 after multiple rounds of iterations, the actual improvement was not as wonderful as announced at the seminar.

Looking back at GAA, TSMC calls it nanosheetFET, and Intel calls it RibbonFET. The essence of these technologies is the same, which is to turn the fin of FinFET 90°, and then stack multiple fins horizontally. These fins all pass through the gate - or are completely surrounded by the gate, so it is called gateallaround. In addition, each flipped fin is like a sheet, and they are all channels, so they are also called nanosheetFET.


From a structural point of view, the contact area between the gate and channel of the GAAFET transistor has become larger, and there is contact on each side, which enables better switching control than FinFET. And for FinFET, the width of the fin is a fixed value; but for GAAFET, the width of the sheet itself and the effective channel width are flexible. A wider sheet will naturally achieve higher drive current and performance, while a narrower sheet will occupy a smaller area.

The reason why TSMC does not use GAA in 3nm is not difficult to understand, cost and technology. The cost is the capital investment in new factories and new facilities, and technology, such as lower hole mobility in silicon-based channels, results in poor pFET performance. IBM stated at the previous IEDM that the solution to this problem lies in the silicon germanium (SiGe) channel material that pFET can apply compressive stress: "The pFET silicon germanium channel can achieve a 40% mobility increase, a 10% performance advantage compared to silicon-based channels, and has a lower threshold voltage (Vt), and the negative bias temperature instability (NBTI) performance is also improved."

Of course, the benefits of GAA are not obvious, which may also be one of TSMC's concerns. Samsung has previously talked about the 3nmGAA process and its advantages over 4nmFinFET in terms of frequency and power consumption, as shown in the figure below, but the figure does not provide absolute and relative values. It only speaks in general terms. Compared with 4nmFinFET transistors, 3nmGAA can achieve higher frequencies under the same effective channel width (Weff, width of fin/sheet × number of fins/sheet); at the same time, it can achieve lower power consumption.


Various reasons made TSMC make up its mind to use GAA only in 2nm. 3nm became the last generation of FinFET, which also paved the way for the overturn of A17Pro.

Of course, the more serious problem is the yield rate. According to data from HiInvestment&Securities, Samsung’s 3nm yield rate is estimated to be more than 60%. In comparison, TSMC’s 3nm yield rate is about 55%. The yield rate of the new technology is almost the same as the yield rate of the old technology, which makes people wonder. The "sweetheart deal" between Apple and TSMC that was exposed a few months ago started: Apple placed a huge order for 3nm chips with TSMC, but required that the costs of substandard chips be borne by TSMC itself. Apple only needs to pay for good chips. Some media said that in this way, Apple can save billions of dollars every year.

If the yield rate is high enough, there is no need for Apple to make a special trip to reach this deal with TSMC. Since TSMC mass-produced 3nm in 2022, the yield rate has still not reached Apple's bottom line, and the energy consumption performance is not ideal now. Whether more customers can be persuaded to accept such a process with prices rising again may be the big problem that TSMC needs to solve in 2024.

Who leads the way in 3nm?

Currently, TSMC still manufactures N3B, the first-generation 3nm process for Apple. The benefit of this process is a significant increase in transistor density, that is, the 19 billion transistors achieved by A17Pro. N3E, which will be launched next year, will be slightly inferior in transistor density, but more ideal in terms of power consumption control. Many manufacturers, including Apple, are interested in adopting this process. If TSMC can significantly improve the yield rate by then, I believe there will still be an endless stream of Fabless manufacturers coming to the door.

But Samsung has already been eyeing GAA's 3nm. Once TSMC makes a mistake, the orders that originally belonged to it may flow to its old rivals. This situation has already happened in 16nm and 7nm. Now that 3nm is pending, there is a possibility that it will happen again.

3nm is a small hurdle that TSMC needs to overcome urgently.