The yield rate of Intel's 18A node is said to be only 10%, and SRAM density also lags behind TSMC.

Intel's ambitious 18A node is facing two major obstacles as it nears mass production: yield rates hover below 10% and SRAM density is at a disadvantage compared to TSMC's competing N2 process. These challenges could hinder the node's deployment in Intel's next-generation portfolio of CPUs, artificial intelligence and custom chips.

Recent reports indicate that Intel is facing huge yield challenges on the 18A node, which may delay its mass production time. According to South Korea’s Chosun Ilbo, the current yield rate is less than 10%, which means that nearly 9 out of 10 chips produced are defective.

This is a significant issue, especially since Intel has canceled the 20A (2nm) process node for foundry customers and shifted resources to the 18A (1.8nm) node. If yields below 10% prove accurate, it's clear that the node will not be suitable for commercial production, at least until significant improvements are made.

Packing transistors into increasingly dense layouts at these cutting-edge nodes is a huge engineering hurdle that affects the entire semiconductor industry. Samsung's foundry yield rate for processes below 3 nanometers is currently below 50%, and the yield rate of its Gate-All-Around (GAA) technology is said to be as low as 10% to 20%.

There is reason to be optimistic about Intel's 18A node, though, as the company still has several months to perfect the process before mass production is expected in 2025. The 18A node will power high-profile products such as Intel server chips, mobile CPUs and custom artificial intelligence chips, and the potential returns are huge.

If Intel can quickly increase the 18A yield rate to a respectable level (over 60%) in the next few months, the node may still drive the development of the company's next-generation products.

Still, yield issues aren't the only challenge Intel faces with 18A. TSMC has also reportedly gained an advantage in another key area: SRAM density.

According to the ISSCC2025 promotion plan, TSMC’s N2 (2nm level) node shrinks the high-density SRAM bit cell to approximately 0.0175μm², with a density reaching 38Mb/mm². In comparison, Intel's 18A node achieved 0.021μm² and 31.8Mb/mm², which is closer to TSMC's previous generation N3E and N5 nodes, which is a clear difference.

As chip designs require more SRAM, increasing the density of these tiny memory cells is critical to maintaining compact, efficient designs. This is where all-gate (GAA) transistors come into play.

Compared with traditional fin field effect transistors (finFETs), GAA transistors achieve tighter scaling by controlling the channels on all sides. This tight control reduces leakage at small sizes, enabling higher-density SRAMs. Both Intel and TSMC are using GAA to shrink their SRAM bits, but TSMC has successfully packed them more densely with its N2 node.