Japan's Rapidus is advancing its 2nm process, there are reportsDow disclosed the logic density of the node for the first time, which is said to be comparable to TSMC’s N2.According to reports, the logic density of Rapidus's 2HP process node has reached 237.31 million transistors/square millimeter (MTr/mm²), which is equivalent to the 236.17 MTr/mm² of TSMC's N2 process.

This data shows that Rapidus's 2HP process is on the same level as TSMC's N2 process in terms of logic density, and even has advantages in some aspects.

The 2nm battle is in a stalemate! Japan’s Rapidus logic density is on par with TSMC N2: surpassing Intel 18A

In comparison, the logic density of Intel's 18A process is 184.21 MTr/mm², which is significantly lower than the levels of Rapidus and TSMC.

Rapidus' 2HP process uses a high-density (HD) cell library with a cell height of 138 units based on G45 pitch, which is designed to achieve maximum logic density.

Intel pays more attention to the performance/power consumption ratio, so higher density is not its main goal, especially the 18A process is mainly for internal use.

The 2nm battle is in a stalemate! Japan’s Rapidus logic density is on par with TSMC N2: surpassing Intel 18A

In addition, Rapidus uses monolithic front-end processing technology, which can focus on adjusting limited production volumes and extending the improvements to the final product. Rapidus plans to provide its 2nm process design kit to customers in the first quarter of 2026.