According to news on December 26, according to Nikkei Asia, as advanced processes continue to advance, the cost of each new process node is increasing, and the increase is getting larger and larger. Analysis by the research organization International Business Strategies (IBS) believes that the cost of the next-generation 2nm process will increase by up to 50% compared to the current 3nm process.Eventually, the price of 2nm wafers will reach US$30,000.
IBS estimates that the cost of building a fab with a monthly production capacity of 50,000 2nm wafers is approximately US$28 billion, while the construction cost of a 3nm fab with the same capacity is approximately US$20 billion.
Among them, the cost increase mainly comes from the increase in the number of expensive ASMLEUV lithography machines.
Because the 2nm process has a more refined transistor structure than the 3nm process, if you want to maintain the original production efficiency, you will inevitably need to use more advanced process manufacturing equipment, and EUV lithography machines are just one of them. Currently, Apple is still the only company using TSMC’s 3nm (N3B) process to mass-produce chips.
IBS further estimates that when Apple launches chips based on TSMC's N2 manufacturing process in 2025 to 2026, processing a single 300mm wafer using TSMC's N2 manufacturing process will cost approximately $30,000, higher than IBS's estimated cost of approximately $20,000 for a single wafer based on TSMC's N3 process.
This significant increase in cost per wafer will inevitably increase the cost of all chips based on this process technology by a similar amount.
In addition, IBS also believes that Apple’s current 3nm chip costs about $50 to manufacture. However, this cost figure is higher than that reported by another research organization.
Arete Research estimates that the Die (chip die) size of Apple's latest 3nm process A17Pro chip is between 100mm^2 and 110mm^2, which is consistent with the chip size of the company's previous generation A15 (107.7mm^2) and A16 (about 5% larger than A15, about 113mm^2).
If the Apple A17Pro's chip size is 105mm^2, then a 300mm wafer can accommodate 586 chips, which makes its cost about $34 at an unrealistic 100% yield and about $40 at a more realistic 85% yield.
At $30,000 per wafer and a yield of 85%, the manufacturing cost of a single 105mm^2 chip is about $60, but this is a very rough estimate. IBS believes that the manufacturing cost of future 2nm "Apple chips" will rise from US$50 to about US$85.
It is worth mentioning that price competition among leading wafer foundries will also affect the final price of 2nm chips. Currently, TSMC, Intel, and Samsung are actively promoting mass production of the 2nm process.
According to the plan, Intel will mass-produce Intel20A in the first half of 2024 and Intel18A in the second half of the year. Both will be based on RibbonFET (similar to GAA) transistor architecture and back-side power supply (PowerVia) technology. It is expected that related products will be launched in the first half of 2025.
TSMC and Samsung both plan to mass produce 2nm processes in 2025. Relative to TSMC's current monopoly in the cutting-edge process wafer foundry market, Samsung and Intel are expected to compete in the market through price wars, which will also lead to a certain extent in which the final pricing of 2nm wafers may deviate from the forecast model.
Of course, the manufacturing cost of a chip is only a part of the total cost of the chip. The development cost of chips with cutting-edge processes is also very high.
According to IBS forecasts, a 2nm chip may require US$314 million in software development alone, and another US$154 million in verification of the chip, plus the cost of purchasing related semiconductor IP, tape-out costs, and the cost of other supporting infrastructure and related services.The total cost may reach US$725 million.
More importantly, chip development in the 2nm process requires more high-end talents, and such high-end talents have always been in short supply. Direct competition from manufacturers will further lead to an increase in talent costs.
It should be noted that the above prediction model is based on a cost prediction model for developing 2nm chips by a chip design company with no pre-existing intellectual property rights.
In reality, manufacturers that can develop cutting-edge process chips like 2nm usually have a relatively large accumulation of self-developed IP, which will reduce the cost of a lot of outsourced IP.
In addition, as EDA manufacturers have added AI support for design tools, AI will be able to automate complex design processes and accelerate chip optimization and verification, thereby reducing chip costs.