Abstract:
MemSilicon announced the completion of the tape-out of the first-generation high-density, large-capacity RRAM chip "MountTai 2026" based on the 1TnR technology route.
It is reported that "Taishan No. 1" is a milestone in MemSilicon's advancement of 1TnR high-density, large-capacity new memory chip technology from early research to the commercialization of Gb-level chips. This technical route increases the storage capacity per unit area by sharing select transistors with multiple resistive switching memory cells, and uses a back-end integration method that is fully compatible with the CMOS platform to achieve both density, capacity and cost.
The chip uses a 28nm CMOS process platform and a 1T4R unit structure, with a single chip capacity of 1Gb, a density of 30Mb/mm², an access delay of less than 20ns, and an integrated on-chip hardware error correction circuit. It achieves a collaborative breakthrough between large capacity, high density and high-speed reading, and provides an internationally competitive solution for on-chip high-density and large-capacity new non-volatile storage applications.
At present, "Taishan No. 1" has completed the tape-out and is advancing verification.
"Taishan No. 1" adopts a 1T4R structure, that is, one selection transistor corresponds to four resistive switching memory cells. But sharing transistors does not mean that the density and performance of the number of memory cells increase proportionally. Non-target current paths between multiple memory cells, read and write interference, and reliability under different operating conditions all require joint optimization of devices, processes, and circuit designs.
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