At the 2023 IEEE International Electronic Devices Meeting (IEDM), Intel researchers demonstrated advanced technology combining three-dimensional stacked CMOS (complementary metal oxide semiconductor) transistors with backside power and direct backside contact. The company also reported expansion paths for its recent R&D breakthroughs in backside power delivery, such as backside contacts, and successfully demonstrated, for the first time, large-scale three-dimensional monolithic integration of silicon transistors with gallium nitride (GaN) transistors on the same 300 millimeter (mm) wafer (rather than a package).
"As we enter the EM era and move past five process nodes in four years, continued innovation is more important than ever. At IEDM2023, Intel showcases the advances it has made in research that are driving Moore's Law, highlighting our ability to bring leading technologies to the next generation of mobile computing, enabling further scaling and efficient power delivery."
Sanjay Natarajan, senior vice president and general manager of Components Research at Intel
Why is it important? Transistor scaling and backside power are key to helping meet the exponential growth in demand for more powerful computing power. Year after year, Intel meets this computing demand, demonstrating that its innovations will continue to drive the semiconductor industry and continue to be the cornerstone of Moore's Law. Intel's component research group continues to push the limits of engineering by stacking transistors, taking backside power to new levels, enabling more transistor scaling and higher performance, and proving that transistors made of different materials can be integrated on the same wafer.
The image on the left shows a design where power and signal lines are blended together on top of the wafer. Shown on the right is the new PowerVia technology, Intel's unique rear-side power delivery network used for the first time in the industry. PowerVia was launched at the Intel Accelerator event on July 26, 2021. At the event, Intel showcased the company's future process and packaging technology roadmap. (Image source: Intel Corporation)
The recently announced process technology roadmap highlights the company's continued expansion of innovations, including PowerVia backside power, glass substrates for advanced packaging and FoverosDirect, all technologies originating from the component research group and expected to enter production this decade.
At IEDM2023, Intel Component Research demonstrated its commitment to innovation by putting more transistors on silicon while achieving higher performance. Researchers have identified key R&D areas needed to continue scaling up by efficiently stacking transistors. Combined with backside power and backside contacts, these will be significant advances in transistor architecture technology. While improving backside power delivery and adopting new 2D channel materials, Intel is working to extend Moore's Law to one trillion transistor packages by 2030.
Intel's latest transistor research results demonstrated at IEDM2023 enable vertical stacking of complementary field-effect transistors (CFETs) with gate pitches as low as 60 nanometers. By stacking transistors, area efficiency and performance advantages can be achieved. It is also combined with backside power and direct back contact. It highlights Intel's leadership in all-gate transistors and demonstrates the company's ability to innovate beyond RibbonFET, putting it ahead of the competition.
Intel has gone through five process nodes in four years and identified key R&D areas needed to continue scaling transistors with backside power transfer: Intel's PowerVia, which will be manufactured in 2024, will be the first to enable backside power transfer. At IEDM2023, Components Research identified pathways to extend and expand backside power delivery beyond PowerVia, as well as the key process advancements required to enable these pathways. Additionally, this work highlights the use of backside contacts and other novel vertical interconnects to enable area-efficient device stacking.