At the recent IEDM conference, TSMC previewed a process roadmap for next-generation chip packaging that can package more than one trillion transistors by 2030. This coincides with Intel's long-term vision. Such huge transistor counts will be achieved through advanced multi-chip set 3D packaging. But TSMC also aims to increase the complexity of monolithic chips, ultimately achieving a design of 200 billion transistors on a single chip.
This requires TSMC to steadily upgrade the planned N2, N2P, N1.4 and N1 nodes. Although multi-chip set architectures are currently gaining traction, TSMC believes that packaging density and raw transistor density must increase simultaneously. NVIDIA's 80 billion-transistor GH100 GPU is one of the largest chips available today, excluding Cerebras' wafer-level design.
However, TSMC's roadmap calls for more than doubling that number, first with monolithic designs of more than 100 billion transistors, and then eventually 200 billion. Of course, as chip size increases, yield becomes more challenging, which is why advanced small chip packaging becomes critical.
Multi-chip module products such as AMD's MI300X and Intel's PonteVecchio have integrated dozens of chips, including 47 chips in PVC. TSMC envisions extending this expansion to chip packages housing more than a trillion transistors through its CoWoS, InFO, 3D stacking and many other technologies.
Although the expansion rate has slowed recently, TSMC is still confident of making breakthroughs in packaging and process to meet future density needs. Continued investment in foundries ensures progress in unlocking next-generation semiconductor capabilities. But no matter how aggressive the roadmap, physics will ultimately dictate the timeline.