Abstract:
He Tingbo, President of Huawei's Semiconductor Business Unit, recently published a paper "Huawei's τ Chip Was Supposed to Melt?" on ChinaXiv, a pre-release platform for scientific papers of the Chinese Academy of Sciences. For the first time, he used actual measured data of mass-produced chips to directly respond to industry doubts that 3D stacking will inevitably generate heat.
The paper disclosed that the transistor density of the Kirin 2026 chip using Logic Folding technology jumped from 155 million to 238 million per square millimeter, an increase of 55%. This increase is equivalent to the results of the miniaturization of traditional crafts over the past three years.
Under the same performance, NPU power consumption dropped by 66%, GPU power consumption dropped by 58%, and CPU performance core power consumption dropped by 41%. When the NPU maintained the same computing power of 29 TOPS, the frequency dropped by 63%, the voltage dropped from 0.85V to 0.55V, and the power density plummeted by 73%.
He Tingbo pointed out that most of the chip's energy consumption is not consumed in transistor calculations, but in data transmission through metal wiring. Logic folding stacks planar circuits vertically and replaces long horizontal traces with very short vertical interconnects. Typical core wiring lengths are shortened by about 20% and critical paths are shortened by up to 70%.
Shortening the traces directly reduces the interconnect capacitance, and the circuit can further reduce the operating voltage. Dynamic power consumption is proportional to the square of the voltage, resulting in greater power consumption gains. The number of clock buffers in a certain module was reduced from 43,600 to 19,000, which was cut by more than half.
In terms of thermal management, Huawei adopts thermal-aware zoning and layout planning strategies. It intentionally avoids folding high-power circuits during the design phase and prevents high-power subsystems from being adjacent in space. The modules that generate the most heat are placed where the heat dissipation path is clearest.
Kirin 2026 is the first mobile SoC to adopt logical folding. Using 1.5 micron hybrid bonding pitch, 50 million vertical interconnects are achieved. Huawei emphasizes that these performance differences come entirely from architectural changes and do not use new photolithography processes.
However, logical folding does not perform consistently on all modules, and the benefits of different computing units vary significantly.
The total power consumption of the DSP module dropped by 25%, but because the chip area was simultaneously reduced by 40%, the power density increased by 24%. Kirin 2027 has solved this problem. However, the benefits of the CPU performance core are relatively limited due to the serial computing characteristics, and the power consumption is reduced by 41%.
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