Abstract:
CXMT is facing a severe yield test on the road to cutting-edge high-bandwidth memory (HBM). According to the technology media wccftech citing industry supply chain surveys and the latest reports disclosed by the Korean industry, Changxin Memory encountered serious process bottlenecks during the trial production of 8-layer stacked HBM3 memory particles for artificial intelligence computing chips. The comprehensive yield rate has been hovering in the low range of 25% to 30% for a long time. If the extremely stringent final packaging and testing and performance evaluation links are superimposed, nearly 80% of the chip products that are offline even fail to pass the final inspection test. The actual comprehensive yield rate faces huge challenges.
As the backbone of China's storage semiconductor industry, Changxin Memory has made significant breakthroughs in the manufacturing of conventional DDR4 and 17nm-level DDR5 memory chips in recent years. Its conventional DRAM yield rate has reportedly exceeded 90%, and it has quickly captured market share in the global mainstream consumer and server memory markets. However, compared with traditional planar single-layer DRAM modules, HBM technology has a huge difference in packaging complexity. It not only requires vertical stacking of multiple DRAM die, but also relies on high-precision through-silicon via (TSV) interconnection, micro-bump welding, and sophisticated advanced packaging materials. This high-threshold manufacturing process places extremely stringent requirements on process control. Any single-layer die defects or micro-interconnect alignment errors will directly lead to the scrapping of the entire expensive HBM stacked chip.
Changxin Memory’s HBM3 chip is mainly manufactured using a 16-nanometer process and adopts an 8-layer vertical stacking architecture. Due to the lack of extreme ultraviolet (EUV) lithography system support, companies have to rely heavily on deep ultraviolet (DUV) multiple exposure solutions with multiple additional process steps, which virtually doubles the defect rate and packaging stress control difficulty. After the wafer manufacturing and preliminary lamination were completed, the rough yield rate was only maintained at about a quarter. In the subsequent final quality evaluation of high-frequency signal integrity, heating power consumption, and long-term stability, only about 70% of the surviving samples could barely meet the standards. As a result, for every 100 HBM3 chips that were rolled off the assembly line, only about 20 could truly meet commercial delivery standards.
In sharp contrast, the three traditional giants in the global HBM market, SK Hynix, Samsung Electronics and Micron Technology, have experienced years of production line polishing. The yield rate of their HBM3 and more advanced HBM3E production lines has steadily climbed to a mature level of 60% or even higher, and they are steadily moving towards the next generation HBM4 architecture. Changxin Memory's current yield rate of about 25% means that the sunk cost of scrapped wafers and materials for manufacturing a single usable HBM chip is extremely high, which directly restricts its pace of large-scale delivery to domestic AI computing power chip customers such as Huawei Ascend, Cambrian and Alibaba Pingtouge.
Although the initial low yield rate has brought huge financial and production capacity loss pressure to Changxin Memory, being able to run through the entire HBM3 physical stacking and proofing process in an environment of strict external export controls and technical blockades still marks that China Semiconductor has crossed the most difficult prototype verification threshold in the field of advanced heterogeneous integration. For Changxin Storage, the core proposition at this stage has shifted from "can it be manufactured" to "how to tackle yield rate." With the continuous fine-tuning of the subsequent stacked hot-press packaging process, the accumulation of experience in production line machine parameters, and the collaborative optimization with local packaging and testing giants, whether Changxin Storage can increase the overall yield rate to an economically feasible break-even line during the planned mass production cycle from the end of 2026 to 2027 will become a key decisive point in determining the self-sufficiency of the domestic AI computing power supply chain.
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