Abstract:
Intel executives recently stated in public interviews that the gap between the company and TSMC in advanced process technology has narrowed to "only a few percentage points." The biggest challenge in catching up with industry leaders in the future is no longer the technology itself, but how to establish a manufacturing scale and production capacity system that matches its competitors.
In the Dwarkesh Podcast, Intel Chief Technology Officer Pushkar Ranade pointed out that from a pure technology and performance perspective, the distance between Intel and TSMC is already quite limited. He believes that the core issue facing the company is to expand the production scale of advanced processes, and this process will take a long time to complete. In other words, what determines the competitive landscape is not only the process node itself, but also who can produce advanced chips stably and economically on a larger scale.
At the same time, Chris Os, vice president and general manager of Intel's manufacturing development and customer cooperation department, focused on the company's layout in high numerical aperture extreme ultraviolet lithography (High-NA EUV) technology. He said that because Intel was the first to adopt Backside Power Delivery technology, the company has a unique advantage when utilizing High-NA EUV equipment.
High-NA EUV is widely regarded as a key technology for next-generation chip manufacturing. Compared with existing EUV equipment, its higher numerical aperture can improve lithography resolution, giving chip manufacturers the opportunity to complete finer circuit patterns with fewer exposure steps. This is expected to not only reduce manufacturing complexity, but also reduce production costs. The report pointed out that this technology can support advanced pattern manufacturing within a pitch range of approximately 8 nanometers to 16 nanometers, providing support for future higher-density chip designs.
Chris Os explained that the backside power supply architecture adopted by Intel transfers the power supply network originally located on the front of the wafer to the back of the wafer, thus freeing up more space for the layout of front-side transistors and data transmission lines. This design effectively reduces the front-end line spacing pressure and allows the chip design to have a looser tolerance space during the photolithography process.
According to him, because of its backside power supply technology, Intel can directly use High-NA EUV to complete related graphics manufacturing. Since TSMC does not adopt the same power supply architecture, it must maintain tighter line spacing in some designs. Therefore, it cannot completely rely on High-NA EUV to complete production. It still needs to rely on dual patterning EUV processes to achieve its goals.
He further revealed that Intel’s next-generation 14A process is currently open to customers as an option in the process design kit (PDK). Regarding whether to adopt this process, the company will conduct individual discussions and cooperation based on the needs of different customers.
The industry believes that this statement further shows that Intel is actively promoting High-NA EUV deployment around the 14A node. There have been rumors in the market that High-NA EUV may first be used in the 18A process, but judging from the information disclosed this time, 14A has become one of Intel's key planning next-generation advanced process platforms.
As competition in the global semiconductor industry continues to heat up, Intel is trying to re-establish its competitive advantage through a combination of technologies such as backside power supply, high numerical aperture EUV and new generation 14A process. Although company executives believe that they are close to TSMC at the technical level, Intel still faces long-term and arduous challenges in terms of large-scale production of advanced processes, customer ecology, and capacity expansion.
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