Abstract:
AMD CEO Su Zifeng demonstrated the next-generation EPYC processor Verano at the 2026 Open Compute Project Global Summit. AMD confirmed that Verano will be the first EPYC product to use the LPDDR memory interface and is planned to be launched in 2027. It will be positioned as an AI server host node processor, responsible for scheduling data and tasks, and providing support for GPU accelerators. AMD's official page positions the EPYC 9006 LP series as AI host nodes, emphasizing improving system energy efficiency and accelerator utilization.
In terms of memory, Verano is described as using LPDDR5X and SOCAMM2 modules. SOCAMM2 is a replaceable low-power memory module that aims to provide higher bandwidth and capacity in limited rack space. However, AMD's announcement only confirmed the LPDDR memory interface and did not announce the final memory type, capacity, channel number, speed or module configuration; the specific combination of LPDDR5X and SOCAMM2 should still be regarded as a specification clue compiled by the media based on previous data and display information, rather than a complete final specification table.
AMD's early disclosures pointed to a maximum of 72 cores in a single-socket Verano, and the newly emerged 192-core statement may represent a single processor or a dual-socket system configuration; there is currently no public specification sheet that can explain whether this number refers to the chip, the dual-socket server, or the entire system. Previous AMD technology preview materials have described Verano as having up to 72 cores and 144 threads, and listed an xGMI interconnect with a maximum frequency of about 5GHz and a maximum of 112Gbps. However, these parameters are also not equivalent to the official mass production model specifications, and the final configuration has yet to be confirmed by AMD when it is released.
The package may include eight sets of computing chips, two large I/O chips and four sets of LPDDR5X controllers, and it is speculated that the computing chips may use standard Zen 6 cores instead of the high-density Zen 6c version. These are interpretations of the appearance of the photos, and AMD has not publicly confirmed the die count or layout. AMD officially only refers to Verano as the sixth-generation EPYC product and stated that it will continue its data center-oriented route; the company has also previously confirmed that Verano will expand TSMC's 2-nanometer process to subsequent EPYC product lines.
Verano will cooperate with the Instinct accelerator and AMD's rack-level system layout for agent-based artificial intelligence, with the goal of assuming the role of the host CPU in the AI server. It is different from the EPYC processor that pursues the highest general-purpose core density, focusing on memory bandwidth, CPU and GPU interconnection, and system-level energy efficiency. In addition to the 2027 launch plan and the adoption of the LPDDR interface, AMD has not announced the final core number, specific memory specifications, power consumption, price or benchmark test results of Verano, so "192 cores" cannot currently be regarded as a confirmed single processor parameter.
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